The present disclosure relates to circuit protection provided by a power clamp and more specifically, to space efficient and power spike resistant ESD power clamp with digitally timed latch.
In today's environment, clamp circuits are used to provide protection to integrated circuits and devices from the buildup and discharge of electrostatic energy. At the onset of an ESD event devices must be able to detect and safely discharge this energy without causing damage to the protected device. Power clamps use RC networks to detect ESD events. RC networks of regular power clamps have to be configured such that their time constants are significantly longer than the 10 ns ESD rise time, while simultaneously being significantly shorter than the normal operation power supply ramp time. For these reasons, a typical RC value is 1 μs and the power supply rise time is restricted to values longer than 100 μs. Achieving a 1 μs time constant requires large resistors and capacitors that have a large footprint. There is a need for space efficient and reliable power clamps to enable the protection of devices with fast power supply ramp times.